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NXP Semiconductors /LPC5410x /SYSCON /PDRUNCFGCLR

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Interpret as PDRUNCFGCLR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0PD_CLR

Description

Clear bits in PDRUNCFG

Fields

PD_CLR

Writing ones to this register clears the corresponding bit or bits in the PDRUNCFG register, if they are implemented. Bits that do not correspond to defined bits in PDRUNCFG are reserved and only zeroes should be written to them.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data